1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile ferroelectric memory device and method for detecting a weak cell using the same.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 shows hysteresis loop of a general ferroelectric. As shown in FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory device will now be described. FIG. 2 shows unit cell of a related art nonvolatile ferroelectric memory.
As shown in FIG. 2, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T1 with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected with a drain of the transistor T1 and a second terminal is connected with the plate line P/L.
In the related art nonvolatile ferroelectric memory including unit cells, weak cells occur due to defect of the ferroelectric capacitor of each unit cell.
To detect such weak cells, an offset sensing amplifying circuit shown in FIG. 3 is typically used. That is, a sensing margin is varied by adding an offset voltage to a sensing voltage of a bit line.
A method for detecting weak cells using the related art nonvolatile ferroelectric memory will be described with reference to the accompanying drawings.
FIG. 3 is a diagram of an offset control circuit of a related art sensing amplifier, and FIG. 4 is a graph showing the variation of an offset voltage according to a bitline voltage during a reading mode of the cell.
As shown in FIG. 3, the offset control circuit of the related art sensing amplifier includes a bitline, a bitline bar, a first inverter, and a second inverter. The first inverter inverts a bitline signal between the bitline and the bitline bar, and the second inverter inverts a bitline bar signal and outputs the inverted signal to the bitline.
A first switching transistor and a first offset capacitor are provided between the bitline and a driver while a second switching transistor and a second offset capacitor are provided between the bitline bar and the driver.
At this time, the first switching transistor transmits the bitline signal to the driver through the offset capacitor while the second switching transistor transmits the bitline bar signal to the driver through the offset capacitor.
The related art method for detecting weak cells is performed using the offset control circuit shown in FIG. 3. In this method, the sensing margin is varied by adding the offset voltage to the bitline sensing voltage.
In other words, addition of an offset to a normal bitline level breaks loading balance of the bitline, and an operational margin of a sensing amplifier is reduced during sensing operation. Thus, weak cells are detected.
FIG. 4 is a graph showing variation of an offset voltage according to a bitline voltage during related art reading mode. Referring to FIG. 4, if the bitline voltage is small during the reading mode, the offset voltage applied to the bitline becomes small. If the bitline voltage is great, the offset voltage becomes grater.
The related art method for detecting weak cells using the related art nonvolatile ferroelectric memory has several problems.
Since a separate offset capacitor is required to detect the weak cells, the process becomes complicated. If the process conditions are varied, a normal bitline level is varied. This may cause an error in detecting the weak cells.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a nonvolatile ferroelectric memory device and method for detecting a weak cell using the same in which a separate test mode is not required, and a weak cell is easily detected and eliminated even if process conditions are varied.
To achieve at least these objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as em bodied and broadly described, a nonvolatile ferroelectric memory device according to the present invention includes: a nonvolatile ferroelectric memory cell driver including a top cell array and a bottom cell array, a sensing amplifier formed between the top and bottom cell arrays, for sensing the top and bottom cell arrays, and a wordline driver for driving a wordline of the top and bottom cell arrays; an X-decoder for selectively outputting a wordline decoding signal to the wordline driver; and a pulse width generating unit for varying a width of a restore pulse PW1 and outputting the varied width to the wordline driver to detect a weak cell of the top and bottom cell arrays.
To further achieve the above objects in a whole or in part according to the present invention, a method for detecting a weak cell using a nonvolatile ferroelectric memory device including a nonvolatile ferroelectric memory cell driver having a top cell array and a bottom cell array, a sensing amplifier for sensing the top and bottom cell arrays, and a wordline driver for driving a wordline of the top and bottom cell arrays, includes the steps of:
selectively outputting a wordline decoding signal to the wordline driver; varying a width of a restore pulse PW1 and outputting the restored pulse having a varied width to the wordline driver to detect a weak cell of the upper and lower cell arrays; controlling data(charge amount) to be stored in a memory cell of each cell array to correspond to the size of the output restore pulse PW1 and outputting bitline sensing levels varied to correspond to the size of the restore pulse; and sensing a memory cell that reaches a minimum sensing level among the varied bitline sensing levels to determine a weak cell.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modification within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.